#ifndef ONBONSOURCE_H
#define ONBONSOURCE_H

#include "../global/ObasicTypes.h"
#include "drv_i2c/drv_i2c.h"

#include <vector>
#include <map>
#include <pthread.h>


#define NUM_REGS_MAX 350

typedef struct Reg_Data{
   unsigned char Reg_Addr;
   unsigned char Reg_Val;
   unsigned char Reg_Mask;
} Reg_Data;


typedef enum{
    init_5338_start,
    init_5338_step1,
    init_5338_step2,
    init_5338_step3,
    init_5338_step4,
    init_5338_step5,
    init_5338_step6,
    init_5338_over
}init_5338;


typedef enum{
    init_s5p210_start,
    init_s5p210_step1,
    init_s5p210_end
}init_S5P210;

typedef enum{
    init_cdce913_start,
    init_cdce913_step1,
    init_cdce913_end
}init_cdce913;

typedef enum{
    init_66121_start,
    init_66121_step1,
    init_66121_step2,
    init_66121_over
}init_66121;

typedef enum{
    init_custom_edid_start,
    init_custom_edid_setup1,
    init_custom_edid_setup2,
    init_custom_edid_setup3,
    init_custom_edid_setup4,
    init_custom_edid_over
}init_custom_edid;

typedef enum{
    onbonsource_init_step_start,
    onbonsource_init_step_setup1,
    onbonsource_init_step_setup2,
    onbonsource_init_step_setup3,
    onbonsource_init_step_over
}init_onbonsource;


typedef enum{
    onbonsource_check_start,
    onbonsource_check_end
}check_onbonsource;


typedef enum{
    OVP_I2C_IO_EXTERN_U27_0x40 = 0x40,
    OVP_I2C_EXTERN_EDID_U34_0xE0 = 0xE0,
    OVP_I2C_EXTERN_S5P210_U34_0xE0 = 0xE0,
    OVP_I2C_EDID_DEVICE_0xA0 = 0xA0,
    OVP_I2C_SOURCE_U31_0xEE = 0xEE,



    OVP_I2C_DEVICE_ADDR_OVER
}OVP_I2C_DEVICE_ADDR;

#if 1//defined(GET_HDMINFO)
typedef struct{
	int Hact;
	int Hsync;
	int Hback;
	int Hpol;
	int Htotal;
	int Vact;
	int Vsync;
	int Vback;
	int Vpol;
	int Vtotal;
	float pfreq; // dot-clock  unit is MHz
	int type; // 0=IT6602  1=IT6807 
	int datamode; // 0=SDR  1=DDR  only for IT6602
	int lane; // number of lanes.  value is 1/2/4/8.  only for IT6807.
	int ip; // 0=progressive  1=interlaced
	int nosignal; // 0=normal  1=no signal
	int stable;   //0:no stable, 1:stable
} ST_HDMIInfo;
#endif



class onbonsource
{
public:
    onbonsource() ;
    ~onbonsource() ;

    static onbonsource* pInstance();
    Oint8 initialize();
    void  onbonsource_deal();

    static onbonsource* p_onbon_source;


    Ouint8 set_custom_volume;
    Ouint8 set_ext_change;
    Ouint8 set_ext_change_step;
    Ouint32 set_ext_change_ticks;


    Ouint8 source_status;



private:

    //ite6805_sys *p_ite6805_sys ;
    Drv_I2C0* p_drv_i2c_0;


    pthread_t m_pidChecksource;

    Ouint8 init_5338_state[2];
    bool init_5338_flag[2];

    Ouint8 init_66121_state;
    //bool init_66121_flag;
    int m_drv_i2c0_fd;

    static  Ouint8  onbon_default_edid_6805[2][256] ;
    static  Ouint8  onbon_default_edid_6602[4][256] ;


private:
    static void * checksourceThread(void * p_check_source);
    static void  sourcecheck(void * p_check_source);


public:
    //about fpga clk(si5338_RevB_Registers.c)
    static Reg_Data const Reg_Store[NUM_REGS_MAX] ;
//    uint32 g_si5338_ic_valid[2];

    //about s5p210 status
    Ouint8 s5p210_ic_valid[2];
    Ouint8 cdce913_ic_valid;
    Ouint8 init_s5p210_state[2];
    Ouint8 init_cdce913_state ;
    bool init_s5p210_flag[2];
    Ouint8 onbonsource_init_step;
    Ouint32 onbonsource_init_ticks;
    Ouint8 source_init_s1;


    void s5p210_setup(int fd, int index);
    void cdce913_setup(int index);


    void it66121_sdi_enable(void);




};




#endif // ONBONSOURCE_H
